Architecture - Texas Instruments OMAP5910 Technical Reference Manual

Architecture

Features / Architecture
1.4 Architecture
1-8
H
Camera interface
H
Five MPUIO general-purpose input/output signals in default
multiplexing mode; five more available through alternative pin
multiplexing modes
H
32-kHz timer
H
Pulse-width tone (PWT) module
H
Pulse-width light (PWL) module
H
Real-time clock (RTC) module
H
Multimedia card (MMC) or serial data (SD) card interface
H
HDQ and 1-Wire serial interface
H
Two light emitting diode (LED) pulse generator modules
H
Frame adjustment counter
J
For the DSP:
H
Three 32-bit timers
H
A 16-bit watchdog timer
H
An interrupt handler
H
McBSP1: Multichannel buffered serial port
H
McBSP3: Multichannel buffered serial port
H
MCSI1: Multichannel serial voice interface
H
MCSI2: Multichannel serial voice interface
J
Shared peripherals:
H
UART1: UART modem with autobaud (16C750 compatible)
H
UART2: UART modem with autobaud (16C750 compatible)
H
UART3: UART modem with IrDA (16C750 compatible)
H
Fourteen general-purpose input/output (GPIO)
H
Mailbox
The OMAP5910 device includes the MPU subsystem, the DSP subsystem, a
memory interface traffic controller, general-purpose peripherals, dedicated
multimedia application (MMA) peripherals, and multiple interfaces. The MPU
is the master of the platform, and it has access to the entire 16M bytes of
memory space and to the 128K bytes of I/O space of the DSP subsystem.
Additionally, the MPU and DSP share access to the internal SRAM and
external memory interfaces.