Memory Maps - Texas Instruments OMAP5910 Technical Reference Manual

Hide thumbs Also See for OMAP5910:

Table of Contents

1.5 Memory Maps

Figure 1–3. MPU Memory Map

Figure 1–3 shows the MPU memory map. Figure 1–4 shows the DSP memory

External slow memory interface

(cs0, cs1, cs2, cs3)

External fast memory interface

Internal SRAM

Internal memory interface

Local bus interface

Reserved (not used for OMAP)

DSP coprocessor interface

TI peripherals and control

peripheral bus

Reserved for HIVECT (high

interrupts vectors)

Introduction