Device Initialization; Emifs Memory Timing Control - Texas Instruments OMAP5910 Reference Manual

3.2.3

Device Initialization

3.2.4

EMIFS Memory Timing Control

SPRU673
Depending on the flash memory or RAM device associated with each chip-
select, the EMIFS interface must be initialized. If the device used is a flash, the
flash may have to be initialized in the correct protocol to achieve maximum
performance.
To use the external flash device with the synchronous flash burst protocol, the
following configuration must be set in the flash device and in the EMIFS
chip-select configuration registers (see Table 14, EMIF Slow Chip-Select
Configuration Registers):
Read mode
-
Frequency configuration
-
Data output configuration
-
Burst order. The EMIFs only supports linear burst order.
-
Burst length
-
CLK configuration
-
Flash mode operation. Some flash modules use multiple signals for
-
burst operations (see Section 3.2.7, Burst Read Operation, for more
information).
After reset, each of the EMIF slow chip-select configuration registers is
configured in the asynchronous mode with 15 wait cycles and a clock divider
of 6 (relative to the traffic controller clock). This configuration ensures
maximum compatibility with many existing devices.
In both asynchronous and synchronous modes all EMIFS-to-memory control
signals are referenced to an internal EMIFS reference clock. The internal
EMIFS reference clock is divided from the TC clock by a programmable value
in the FCLKDIV bit field of the EMIFS chip select configuration register
(EMIFS_CSx_CONFIG). This allows the EMIFS to accommodate timing
constraints of slow devices, even with high system clock rate. Table 5 shows
FCLKDIV settings and resulting EMIFS reference clock values.
Table 5. FCLKDIV Settings and Resulting EMIFS Reference
Clock
FCLKDIV
00
01
EMIFS Reference
TC clock/1
TC clock/2
Memory Interface Traffic Controller
Memory Interfaces
25