Idle Control And Idle Status Registers (Icr And Istr) - Texas Instruments OMAP5910 Technical Reference Manual

3.5.2

Idle Control and Idle Status Registers (ICR and ISTR)

-
Time-out[6:0]
This field specifies the number of cycles that can elapse before the TIPB
returns a bus error condition. The seven-bit field specifies the number of wait
states. The time-out period is determined as
Time-out = value of time out[6:0] + 2 measured in DSP subsystem master
clock cycles
The default value is 0x7f (127).
To conserve power, the DSP subsystem is capable of idling certain circuits.
The DSP CPU and peripherals comprise several clock domains that can be
turned off individually to conserve power. The active/idle status of the various
domains is controlled by the idle control register. When the DSP software
executes the IDLE instruction, the clock domains are configured according to
the settings of the ICR (see Table 3–9). The current idle domain status is
reflected by the state of the ISTR (see Table 3–10).
The idle domains are:
0 CPU
1 DMA
2 Cache
3 Peripherals
4 DPLL
5 EMIF
The DSP DPLL is controlled by the MPU subsystem. When entering low-pow-
er mode requiring DSP DPLL off, the DSP sets DPLL idle domain on followed
by the MPU actually idling the DPLL source by writing the appropriate control
registers (see Chapter 15, Clock Generation and System Reset Management).
The DSP must not attempt to read the ISTR while DPLL domain is
idled, because this causes a time-out error.
TIPB Bridge
DSP Subsystem 3-31