Mmc/Sd Command Response Register 0 (Mmc_Rsp0) - Texas Instruments OMAP5910 Technical Reference Manual

Table 7–115. MMC/SD Command Response Register 0 (MMC_RSP0)
Bit Name
15 – 0 RESP0
Table 7–116. MMC/SD Command Response Register 1 (MMC_RSP1)
Bit Name
15–0 RESP0
Table 7–117. MMC/SD Command Response Register 2 (MMC_RSP2)
Bit Name
15–0 RESP0
Table 7–118. MMC/SD Command Response Register 3 (MMC_RSP3)
Bit Name
15 –0 RESP0
Table 7–119. MMC/SD Command Response Register 4 (MMC_RSP4)
Bit Name
15 –0 RESP0
Table 7–120. MMC/SD Command Response Register 5 (MMC_RSP5)
Bit Name
15 – 0 RESP0
Table 7–115 through Table 7–122 describe 16-bit registers that hold specified
bits positions for a 128-bit response of type R2.
Description
CMD response (R2[15:0])
Description
CMD response (R2[31:16])
Description
CMD response (R2[47:32])
Description
CMD response (R2[63:48])
Description
CMD response (R2[79:64])
Description
CMD response (R2[95:80])
MMC/SD Host Controller
MPU Public Peripherals 7-159