Lcd Channel Usage Restrictions - Texas Instruments OMAP5910 Technical Reference Manual

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Table of Contents

LCD Dedicated Channel

LCD Channel Usage Restrictions

Exclusive Frames

Both Frames Must Belong to a Single Source

LCD Registers Must Remain Steady From One Transfer to Another

FIFO Out of Data (Bandwidth Break)

BF2 is bottom address for frame 2.

TF1 is top address for frame 1.

TF2 is top address for frame 2.

DFM is the dual-frame mode.

In other words, the next address is always the current address + 2 unless the

frame boundaries (inclusive) have been reached (address is a byte address;

it is necessary to increment by two, because all LCD transfers are 16 bits). In

this case, the next address computed is the top address for the frame 1 if in

single frame mode; otherwise, the top address for frame 2 is loaded.

The hardware design does not support inclusion of a frame buffer into another

frame buffer; that is, the start and stop address of each buffer must represent

two different physical parts into the memory. In dual-frame mode the top

address for the second frame must be greater (and not equal) than the bottom

address of the first frame.

In case of dual-frame operation it is not possible to have one frame read from

one source and one frame read from second source. For changing from one

source to another, the LCDEN bit of the LCD control register (see Section 11.8,

LCD Controller Registers) must be cleared to 0 and all pending LCD interrupts

processed. The LCDEN bit level is connected to the dma_lcd_en input of the

DMA LCD channel module as pictured in Figure 5–10.

It is not possible to change any bit of the LCD channel registers until a transfer

has been fully completed. No shadow registers exist in the LCD channel as in

generic channels. Changing bits before transfer completion has not been

tested; results of doing so are unknown. To update registers, the LCDEN bit

should be cleared to 0 and all pending LCD interrupts processed.

FIFO reads are controlled by a state machine that provides the flow control for

the LCD controller. In case of a time-out or bus error while reading the source

memory, the state machine detects the error and does not allow read activity