Mmu Idle Control Register (Dspmmu_Idle_Ctrl); Field Descriptions - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
Table 42. MMU LSB RAM Entry Read Register (READ_RAM_L_REG)

Field Descriptions

Bits Field
31−16 Reserved
15−10 PHYS_TAG_L
9−8 AP
7−0 Reserved
6.5.17

MMU Idle Control Register (DSPMMU_IDLE_CTRL)

Figure 63. MMU Idle Control Register (DSPMMU_IDLE_CTRL)
31
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Table 43. MMU Idle Control Register (DSPMMU_IDLE_CTRL) Field Descriptions
Bits Field
31−2 Reserved
1 GL_PDE
0 AUTOGATING_EN
120 DSP Subsystem
Value Description
These bits are not used.
These are the least-significant bits of the physical address tag
corresponding to the TLB entry. The PHYS_TAG bits correspond to
bits 31−10 of the physical memory address.
Access permission bits. These bits determine the access permission
for the physical memory covered by the TLB entry.
00 or No access.
01
10 Read-only access.
11 Full access.
These bits are not used.
The Idle Control Register controls the DSP MMU clock.
Reserved
R-0
Value Description
These bits are not used.
Global power-down enable bit. This bit is used to shut down the clock
feeding the DSP MMU module.
0 The DSP MMU clock is running.
1 The DSP MMU clock is disabled.
Autogating enable bit
0 Autogating is disabled.
1 Autogating is enabled.
2 1
GL_PDE AUTOGATING_EN
R-0
0
SPRU890A