Dma Source And Destination Parameters Register (Dmacsdp) - Texas Instruments OMAP5910 Reference Manual

DSP DMA
Table 65. DMA Status Register (DMACSR) Field Descriptions (Continued)
Bits Field
2 HALF
1 DROP
0 TIMEOUT
7.3.7

DMA Source and Destination Parameters Register (DMACSDP)

174 DSP Subsystem
Value Description
Half frame status bit. The DMA controller sets HALF only if
HALFIE = 1 in DMACICR and the first half of the current frame has
been transferred from the source port to the destination port. For a
frame with an odd number of elements, the half-frame event occurs as
soon as the number of elements transferred is greater than the
number that remains to be transferred. For example, for a frame of five
elements, the half-frame event occurs when the DMA controller has
transferred three of the elements.
0 The half-frame event has not occurred yet, or HALF has been cleared.
1 The first half of the frame has been transferred. A channel interrupt
request has been sent to the DSP core.
Synchronization event drop status bit. An error occurs if a DMA
synchronization event occurs again before the DMA controller has
finished servicing the previous DMA request. This error is called a
synchronization event drop. The DMA controller sets DROP only if
DROPIE = 1 in DMACICR and a synchronization event drop has
occurred in the channel.
0 A synchronization event drop has not occurred, or DROP has been
cleared.
1 A synchronization event drop has occurred. A channel interrupt
request has been sent to the DSP core.
Timeout status bit. The DMA controller sets TIMEOUT only if
TIMEOUTIE = 1 in DMACICR and a timeout error has occurred at the
source port or the destination port of the channel. The timeout error
conditions are described in section 7.2.15.3.
0 A timeout error has not occurred, or TIMEOUT has been cleared.
1 A timeout error has occurred. A bus-error interrupt request has been
sent to the DSP core.
Each channel has a source and destination parameters register of the form
shown in Figure 86. This I/O-mapped register enables you to choose a source
port (SRC) and a destination port (DST), specify a data type (DATATYPE) for
port accesses, enable or disable data packing (SRCPACK and DSTPACK),
and enable or disable burst transfers (SRCBEN and DSTBEN). Table 66
describes the fields of this register.
SPRU890A