Mmu Address Translation; Mmu Architecture - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
6.2

MMU Architecture

6.2.1 Summary of Address Translation Process
Figure 24.

MMU Address Translation

DSP external memory
space (virtual memory)
68 DSP Subsystem
As shown in Figure 24, the MMU translates virtual addresses generated by the
DSP EMIF to physical addresses. These physical addresses are used to
access the actual OMAP resource.
address translation
Whenever an address translation is requested (that is, for every memory
access with the DSP MMU enabled), the DSP MMU checks first to see whether
the TLB contains the requested translation. The TLB acts like a cache, storing
recent translations.
If the translation is contained in the TLB and the access permissions are correct,
the corresponding physical address is calculated and the memory request is
forwarded to the traffic controller. If the memory request lacks the correct access
permissions, the MMU generates a fault interrupt to the MPU core.
When the requested translation is not in the TLB, the table walking logic (if
enabled) retrieves the translation by reading a set of translation tables. If the table
walking logic is disabled, the MMU generates a fault interrupt to the MPU core.
When the table walking logic finds a valid translation, it updates the TLB and,
if the access permissions are correct, the corresponding physical address is
calculated and the memory request is sent to the traffic controller. If the request
does not have the correct permissions, or if no valid translation is found in the
translation tables, then the MMU generates a fault interrupt to the MPU core.
Figure 25 summarizes the entire DSP MMU translation process.
MMU
OMAP memory space
(physical memory)
SPRU890A