Asynchronous Page Mode Read Operation; Asynchronous 16-Bit Read Operation On A 16-Bit Width Device - Texas Instruments OMAP5910 Reference Manual

Figure 3.

Asynchronous 16-Bit Read Operation on a 16-Bit Width Device

TC Clock
(internal)
EMIFS Ref
(internal)
FLASH.CLK
FLASH.CS_[X]
FLASH.ADV
FLASH.A(24:1)
FLASH.D(15:0)
FLASH.OE
FLASH.BE(1:0)
FLASH.RDY
3.2.6

Asynchronous Page Mode Read Operation

SPRU673
The asynchronous page mode read operation is similar to the asynchronous
read, except that the number of wait states is different between the first access
and the subsequent accesses within the page.
This mode of operation is selected by programming the following fields of the
EMIF slow chip-select configuration registers (see Table 14, EMIF Slow
Chip-Select Configuration Registers).
RDMODE selects the memory type and number of words per page for
-
page mode devices; supported values for words per page are 4, 8, or 16.
RDWST sets the delay to insert prior to latching the first data word read
-
from a page (range 0-15). The resulting delay is equal to (RDWST+2) x
EMIFS_ref. This is represented by N cycles in Figure 4 and Figure 5.
When crossing a page boundary, as in Figure 5, the RDWST parameter
is used again for the first access on the new page.
PGWST sets the delay between subsequent words in the page (range
-
0-15). The resulting delay is equal to (PGWST+1) x EMIFS_ref. This is
represented by P cycles in Figure 4 and Figure 5.
BW defines the word length of the access, which is equal to the memory
-
data bus width.
Low
N cycles
Address valid
High
Memory Interface Traffic Controller
Memory Interfaces
Valid data D0
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