Receive DMA Transfers
Figure 9–15. Receive DMA Transfers
TI peripheral bus
dma add
Ad0
Ad1
dma data
Val0
dum
A receive DMA transfer is initiated after the reception of the last channel of a
frame, at which time all receive registers RX_REG have been updated and are
ready to be read. If N channels are used, the DMA controller successively
accesses all consecutive registers between RX_REG(0) and RX_REG(N-1).
If some channels between RX_REG(0) and RX_REG(N-1) are not used, the
DMA controller reads dummy values when addressing these unused registers
(see Figure 9–15).
ad
Adn
n-1
dum
Valn
A multichannel application cannot use DMA for some channels and interrupt
servicing for others. RX/TX interrupts are not generated when DMA RX/TX
transfers are enabled.
MCSI
MCSI Rx
MCSI Rx
registers
shift
registers
Value 0
Value 0
Dummy 1
Empty 1
Dummy n-1
Empty n-1
Value n
Value n
Empty n+1
Empty n+1
Empty N
Empty N
DSP Public Peripherals
Multichannel Serial Interfaces
Serial input
Value 0 Value n
9-37