Format Of The Fault Address Register; Cache Operations - Texas Instruments OMAP5910 Technical Reference Manual

Figure 2–5. Format of the Fault Address Register
31
2.6.2.2

Cache Operations

Table 2–10. Cache Operations
Function
Flush I- and D-cache
(1)
Flush I-cache
Flush I-cache entry
(1, 2)
Flush D-cache
(2)
Flush D-cache entry
Clean D-cache entry
Clean and flush D-cache entry
(2)
Flush D-cache entry
Notes: 1) Flush I- and D-cache operations invalidate all entries in the I-cache and D-cache respectively. The flush D-cache
also discards any dirty lines present in the D-cache.
2) The flush D-cache and D-cache entry operations do not clean the D-cache entries before they are invalidated.
A clean and flush D-cache requires two cache operations; there is a specific operation for cleaning and flushing
a D-cache entry at once. First clean then flush the entire cache; this requires two CP15 operations (bear in mind
the VIVT clean algorithm). You can clean and flush individual entries in one CP15 operation.
3) Figure 2–6 shows the format of the Rd value for all D-cache operations on a single entry.
4) TI925T supports high performance full cache clean operation with the VIVT algorithm.
Fault Address
Reading CP15 register 6 returns the value of the fault address register (FAR).
The FAR holds the virtual address of the access that was attempted when a
fault occurred. The FAR is only updated for data access faults, not for instruc-
tion fetch faults. When a fault occurs during a load or store multiple (LDM or
STM instructions), the FAR records the domain corresponding to the first fault
caused by LDM or STM (see example in FSR section above).
The CRm and opcode_2 fields are SBZ when reading this register. Writing
CP15 register 6 sets the fault address register to the value of the data written.
The CRm and opcode_2 fields are SBZ when writing to this register.
The CP15 register 7 is a write-only pseudoregister managing the instruction
and data caches. Several cache operations are defined and are selected by
the opcode_2 and CRm fields.
Opcode_2 CRm
0b000 0b0111
0b000 0b0101
0b001 0b0101
0b000 0b0110
0b001 0b0110
0b001 0b1010
0b001 0b1110
0b010 0b0110
Rd Instruction
SBZ MCR p15, 0, Rd, c7. c7, 0
SBZ MCR p15, 0, Rd, c7, c5, 0
VA MCR p15, 0, Rd, c7, c5, 1
SBZ MCR p15, 0, Rd, c7, c6, 0
VA MCR p15, 0, Rd, c7, c6, 1
VA MCR p15, 0, Rd, c7, c10, 1
VA MCR p15, 0, Rd, c7, c14, 1
(3)
Set/Index MCR p15, 0, Rd, c7, c6, 2
MPU Subsystem
Coprocessor 15
0
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