Hardware Acceleration Modules - Texas Instruments OMAP5910 Technical Reference Manual

3.2.1.1 Power Conservation
3.2.2

Hardware Acceleration Modules

3.2.3 CPU Overview
Features include:
-
Software-programmable
low-power modes
-
Automatic power management
-
Advanced low-power complimentary metal-oxide semiconductor (CMOS)
process
The OMAP5910 device contains several hardware acceleration modules to
improve performance and reduce power consumption for certain computa-
tions relating to image and video processing. These coprocessors include:
-
DCT/IDCT accelerator
-
Motion estimation calculation accelerator
-
Half-pixel interpolation accelerator
The DSP core has four functional units:
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The instruction unit (IU) loads, parses, queues, and decodes instructions
and includes an instruction buffer unit (IBQ) to decouple the program fetch
function from the pipeline.
-
The program flow unit (PU) coordinates program actions among multiple
parallel CPU functional units.
-
The address data flow unit (AU) provides data address generation and in-
cludes a 16-bit arithmetic unit capable of performing arithmetic, logical,
shift, and saturation operations.
-
The data computation unit (DU) contains the primary computation units of
the CPU including a 40-bit arithmetic logic unit, two multiply-accumulate
units (MACs), and a shifter.
To permit high computational throughput and a fast instruction cycle rate, the
CPU employs several sets of parallel buses to access code and data struc-
tures. The program address and data buses (P-bus) perform 32-bit instruction
fetches to feed the instruction unit. The B, C, and D addresses and data buses
enable the CPU to access up to three 16-bit data operands per cycle. E and
F addresses and data buses allow the CPU to write up to two 16-bit quantities
per cycle.
Figure 3–4 shows the C55x DSP architecture.
TMS320C55x DSP CPU Overview
idle domains that
DSP Subsystem
provide configurable
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