Instruction Presence Check And I-Cache Response - Texas Instruments OMAP5910 Reference Manual

4.2.3.2 Instruction Presence Check and Corresponding I-Cache Response
Table 4.

Instruction Presence Check and I-Cache Response

Case 2-Way Case
1 Miss
(no tag match)
2 Miss
3 Miss
4 Hit
(no tag match)
5 Hit
6 Hit
SPRU890A
When a fetch request arrives, the I-Cache performs an instruction presence
check to determine whether the 32-bit requested word is available in the
I-Cache. During the instruction presence check, the I-Cache performs two
operations on both the 2-way cache and the RAM sets:
1) Compares the tag portion of the fetch address with the tag in the data array
at the location referenced by the Index portion of the fetch address.
2) Checks the line valid bit at the referenced location to determine whether
the line associated with the tag is valid.
If the tag comparison fails and/or the line valid bit is 0, this qualifies as a miss.
If the instruction presence check finds a tag match and the line valid bit is 1,
this qualifies as a hit. Table 4 summarizes the possible presence check cases
(1 through 6) and the corresponding I-Cache responses. Whenever a line in
the I-Cache must be loaded from DSP external memory (cases 1, 2, and 5),
the I-Cache uses the line load process described in section 4.2.3.3.
RAM Sets Presence
Miss True
Miss True
but tag match
Hit True
Miss True
Miss True
but tag match
Hit True
I-Cache Response
2-way cache line loaded from DSP external memory,
requested 32-bit word delivered to DSP core
RAM set line loaded from DSP external memory,
requested 32-bit word delivered to DSP core
Requested 32-bit word taken directly from RAM set;
2-way cache line not loaded
Requested 32-bit word taken directly from 2-way cache
RAM set line loaded from DSP external memory,
requested 32-bit word delivered to DSP core
Requested 32-bit word taken directly from RAM set
Instruction Cache
DSP Subsystem 37