Introduction To The Dsp Core - Texas Instruments OMAP5910 Reference Manual

C55x DSP Core Overview
2.2

Introduction to the DSP Core

22 DSP Subsystem
The DSP core supports an internal bus structure composed of one program
bus, three data read buses, two data write buses, and additional buses
dedicated to peripheral and DMA controller activity. These buses provide the
ability to perform up to three data reads and two data writes in a single cycle.
The DSP core provides two multiply-accumulate (MAC) units, each capable
of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic
unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under
instruction set control, providing the ability to optimize parallel activity and
power consumption. These resources are managed in the address unit (AU)
and data unit (DU) of the DSP core.
The DSP core supports a variable byte width instruction set for improved code
density. The instruction unit (IU) performs 32-bit program fetches from internal
or DSP external memory and queues instructions for the program unit (PU).
The program unit decodes the instructions, directs tasks to AU and DU
resources, and manages the fully protected pipeline. Predictive branching
capability avoids pipeline flushes on execution of conditional instructions.
Figure 3 shows a conceptual block diagram of the DSP core. Detailed
information on each of the buses and units represented in this figure are given
in the TMS320C55x DSP CPU Reference Guide (SPRU371).
SPRU890A