Dma Controller Configuration Registers - Texas Instruments OMAP5910 Technical Reference Manual

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Table of Contents

DMA Controller Configuration Registers

Table 3–5. DMA Controller Configuration Registers

Table 3–5 lists the DMA controller configuration registers.

Global control

Global time-out control

Global software incompatible control

Channel 0 source destination parameters

Channel 0 control

Channel 0 interrupt control

Channel 0 status

Channel 0 source start address, lower bits

Channel 0 source start address, upper bits

Channel 0 destination start address, lower bits

Channel 0 destination start address, upper bits

Channel 0 element number

Channel 0 frame number

Channel 0 source frame index

Channel 0 source element index

Channel 0 source address counter

Channel 0 destination address counter

Channel 0 destination element index

Channel 0 destination frame index

Channel 1 source destination parameters

Channel 1 control

Channel 1 interrupt control

DMA Controller

Word Address

DSP Subsystem