Data Debug Register Msb (Data_Debug_High) - Offset: X18; Debug Control Signals Register (Debug_Cntr_Sig) - Offset: X1C - Texas Instruments OMAP5910 Technical Reference Manual

MPU TI Peripheral Bus Bridges
Table 2–67. Data Debug Register MSB (DATA_DEBUG_HIGH) – Offset: x18
Bit Description
15–0 Bytes 31–16 of data bus from MPU
Table 2–68. Debug Control Signals Register (DEBUG_CNTR_SIG) – Offset: x1C
Bit Description
8 Burst access
7–6 Peripheral memory access size on TIPB
5–4 Memory access size on TIPB
3 Not supervisor mode on TIPB
2 Read not write on TIPB
1 Flag set to 1 when there is a mismatch between memory
access size and peripheral memory access size.
0 Flag set to 1 when TIPB access is aborted.
2-70
Size Access
16 R 0xFFFF
Size Access
1 R
1 R
1 R
1 R
1 R
1 R
1 R
Reset
Value
Reset
Value
0
3
3
1
0
0
0