Fifo Buffer Parts; Clock Ratios - Texas Instruments OMAP5910 Technical Reference Manual

Figure 7-8. FIFO Buffer Parts
7.2.1.6 Clock Divider
Table 7-1. Clock Ratios
TIPB
When the threshold value is set to 0, the interrupt is generated immediately.
This is the equivalent of the threshold always being exceeded regardless of
whether any data is present in the FIFO.
The clock divider takes the internal 12-MHz clock source or the 48-MHz source
from DPLL to generate the external clock CAM.EXCLK. The division factor is
programmable in the clock control register through FOSCMOD (see
Table 7-1).
Ratio
1
1/2
1/5
1/6
A request is automatically generated to wake up the DPLL when 48 MHz is
needed. The switch is performed when the 48-MHz signal is stable.
It is assumed that the switch is made when CAM.EXCLK is disabled (glitch
protection).
32
Buffering Word y
Buffering Word Q
Buffering Word I
Block Word 1
32
CAM.EXCLK
From 12 MHz
12 MHz
6 MHz
-
-
MPU Public Peripherals
Camera Interface
CAMERA
DMA_REQ
From 48 MHz
-
24 MHz
9.6 MHz
8 MHz
7-9