I-Cache N-Way Control Register (Nwcr); I-Cache N-Way Control Register (Nwcr) Field Descriptions; I-Cache Ram Set Control Registers (Rcr1 And Rcr2) - Texas Instruments OMAP5910 Reference Manual

Figure 14.

I-Cache N-Way Control Register (NWCR)

15
7
Reserved
R-0
Note: R = Read, W = Write; −n = Value after reset;, −x = Value after reset is not defined
Table 9.

I-Cache N-way Control Register (NWCR) Field Descriptions

Bits Field
15−5 Reserved
4−2 WAY_SIZE
1 FLUSH
0 ENABLE
4.6.5

I-Cache RAM Set Control Registers (RCR1 and RCR2)

SPRU890A
Reserved
5 4
Value Description
These bits are not used.
These bits set the size of each way in the N-way cache. The size must
always be set to 8Kbytes.
011b Each way size is set to 8Kbytes.
This bit determines whether the N-way cache is flushed when the
CACLR bit of the DSP core ST3_55 register is set. These bit is ignored
(N-way cache is always flushed) when GLOBAL_FLUSH is set.
0 The N-way cache is not flushed when CACLR is set.
1 The N-way cache is flushed when the CACLR is set.
This bit determines whether the N-way cache is enabled when the
CAEN bit of the DSP core ST3_55 register is set. This bit is ignored
(N-way cache is always enabled) when GLOBAL_ENABLE is set.
0 The N-way cache is not enabled when CACLR is set.
1 The N-way cache is enabled when the CACLR is set.
Each RAM set control register contains two initialization fields and a tag-valid
bit.
Initialization fields (FLUSH and ENABLE). If you have selected one RAM
-
set with the global control register, you must initialize the logic for RAM set
1 before you enable the I-Cache. If you have selected two RAM sets with
the global control register, you must also initialize the logic for RAM set 2.
To perform the initialization for each RAM set, write the appropriate value
(000Fh) to its RAM set control register before enabling the I-Cache.
R-0
2
WAY_SIZE
RW-11
Instruction Cache
8
1 0
FLUSH ENABLE
RW-0 RW-1
DSP Subsystem 53