Tlb Entry Structure - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
6.2.2.1 TLB Entry Format
Figure 26.

TLB Entry Structure

Virtual address tags
(14 bits)
Virtual address tag 31
31
Virtual address tag 30
30
Virtual address tag 2
2
Virtual address tag 1
1
Virtual address tag 0
0
70 DSP Subsystem
Entries in the TLB can be protected, or locked, against being overwritten if
necessary. A maximum of 31 of the 32 TLB entries can be user-written and
protected. One entry must always remain unprotected for use by the table
walking logic. Section 6.2.2.4 describes the locking process, while section
6.2.2.2 describes the process for writing entries into the TLB.
When time-critical program routines are used, it is preferable to avoid the
performance impact of retrieving the translations via table walking logic by
locking TLB entries.
The MPU core can manually write address translations to the TLB.
Alternatively, table walking logic can be used to automatically carry out the
address translation (using the translation tables) and update the TLB.
The TLB entries can be read to determine the currently buffered translations
(section 6.2.2.5). Unused translations can be deleted (section 6.2.2.6).
TLB entries consist of two parts:
CAM. Contains a virtual address tag used to locate the translation in the
-
TLB. The TLB acts as a fully associative cache addressed by the virtual
address tag. The CAM part also contains the memory block size (section,
large page, small page, or tiny page) and the preserved and valid flags.
RAM. Contains the address translation that belongs to the virtual address
-
tag. It also contains the access permissions (no access, read-only access,
and full access).
The TLB entry structure is shown in Figure 26.
CAM part
Preserved bits Valid bits
(1 bit) (1 bit)
P P V V
P P V V
...
P P V V
P P V V
P P V V
0 = Not preserved 0 = Not valid
1 = Preserved 1 = Valid
Physical address tags
Size bits
(2 bits)
S
Physical address tag 31
S
Physical address tag 30
S
Physical address tag 2
S Physical address tag 1
S
Physical address tag 0
00 = Section
01 = Large page
10 = Small page
11 = Tiny page
RAM part
Access
permission
(22 bits)
bits (2 bits)
AP AP
AP AP
AP AP
AP AP
AP AP
0X = No access
10 = Read only
access
11 = Full access
SPRU890A