Irq Binary-Coded Source Register (Sir_Irq) - Texas Instruments OMAP5910 Technical Reference Manual

Interrupt Handlers
Table 8–25. IRQ Binary-Coded Source Register (SIR_IRQ)
Bit Name
3–0 IRQ_NUM
Table 8–26. FIQ Binary-Coded Source Register (SIR_FIQ)
Bit Name
3–0 FIQ_NUM
8-22
The mask interrupt register (MIR) operates after interrupt input register (ITR);
this means that occurrences of incoming interrupts are always stored in
interrupt input register (ITR).
This register saves software processing time by recognizing the interrupt
number as being either an IRQ or FIQ request. Reading this register clears the
corresponding bit in the interrupt input register (ITR) if the interrupt is set as
edge-sensitive. This register will not normally be used since all level 2 DSP
interrupts must be configured as FIQ to generate DSP interrupts because IRQ
is not connected.
In order to save software processing time, this register indicates the interrupt
number that has an IRQ or FIQ request. Reading this register clears the corre-
sponding bit in the interrupt input register (ITR) if the interrupt is set as
edge-sensitive.
Reset
Type
Value
R 0
Reset
Type
Value
R 0