Control Register (Cntl_Reg) Field Descriptions; Mmu Fault Address Registers (Fault_Ad_H_Reg, Fault_Ad_L_Reg) - Texas Instruments OMAP5910 Reference Manual

Table 24. Control Register (CNTL_REG) Field Descriptions
Bits Field
31−3 Reserved
2 TWL_EN
1 MMU_EN
0 MMU_RESET
6.5.5

MMU Fault Address Registers (FAULT_AD_H_REG, FAULT_AD_L_REG)

SPRU890A
Value Description
These bits are not used.
Enables the table walking logic.
Note: When the table walking logic is enabled, the TLB cannot be manually
updated; you should not write to the LD_TLB_REG, TTB_H_REG,
TTB_L_REG, and LOCK_REG.
0 Table walking logic is disabled; access to the TLB is permitted.
1 Table walking logic is enabled; access to the TLB is not permitted.
Enables the MMU.
Note: Before enabling the MMU, you must reset it using the MMU_RESET
bit.
0 The MMU is disabled.
1 The MMU is enabled.
Resets the MMU module. Writing a 0 to this bit resets the MMU to its
default configuration.
Note: You must clear this bit before enabling the MMU.
0 The MMU is in reset.
1 The MMU has been reset successfully.
When a fault is generated, the fault address registers are used to determine
the virtual address that generated the fault. The eight most-significant bits of
the 24-bit virtual address are displayed in FAULT_AD_H_REG, while the rest
of the address bits are displayed in FAULT_AD_L_REG.
To determine the type of fault generated, see the Fault Status Register
(FAULT_ST_REG) in section 6.5.6.
DSP Memory Management Unit
DSP Subsystem 105