Highlight Of Public Peripherals Area - Texas Instruments OMAP5910 Technical Reference Manual

Introduction
9.1 Introduction
Figure 9–1. Highlight of Public Peripherals Area
OMAP5910
32
E
Flash and
16 M
SRAM I
F
memories
S
E
16
M
Memory interface
SDRAM
I
memories traffic controller (TC)
F
F
I
M
I
F
32
32
SRAM
1.5M bits
JTAG/
emulation
I/F
9-2
The four DSP public peripherals for the OMAP5910 processor include two
multichannel buffered serial ports (McBSPs) and two multichannel serial
interfaces (MCSIs):
-
McBSP1
-
McBSP3
-
MCSI1
-
MSCI2
Figure 9–1 shows the OMAP5910 device with the DSP public peripherals
highlighted.
TMS320C55x DSP
(Instruction cache, SARAM
DSP DARAM, DMA,
32
H/W accelerators)
MMU
Interface
32
MPU Bus
32
32
32
System
DMA
32
controller
MPU core
16
(TI925T)
(instruction
cache, data
Clock and reset management
cache, MMU)
LCD
I/F
OSC
ETM9
12 MHz
DSP private
Private peripherals
peripheral bus
Watchdog timer
16
interrupt handlers
DSP public (shared) pheripheral bus
16
16
MPU
32
MPU
peripheral
32
bridge
32
MPU privatePeripherals bus
32
MPU private peripherals
Level 1/2 interrupt handlers
OSC Configuration registers
Device identification
Reset External clock
Clock
32 kHz
request
DSP
Timers (3)
DSP public peripherals
Level 1/2
McBSP1
McBSP3
MCSI1
MCSI2
MPU/DSP shared peripherals
GPIO I/F
TIPB
switch
UART3 IrDA
MPU public peripherals
McBSP2
USB Host I/F
MPU public
peripherals bus
USB Function I/F
2
I C
µWire
Camera I/F
MPUIO
32-kHz timer
PWT
PWL
Keyboard I/F
MMC/SD
LPG x2
Frame adjstument
counter
Timers (3)
HDQ / 1-WIRE
Watchdog timer
RTC
Mailbox
UART1
UART2