Mmc Number Of Blocks Register (Mmc_Nblk) - Texas Instruments OMAP5910 Technical Reference Manual

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Table 7–108. MMC Number of Blocks Register (MMC_NBLK)

Number of Blocks (NBLK)

This register configures the number of blocks for a multiple block data transfer

(read or write) operation for MMC/SD cards. This register is not used for SPI

Number of blocks value

MMC/SD mode only.

In MMC/SD mode, this 11-bit value (bits 10-0) specifies the number of blocks

for a multiple block data transfer (read or write). Each block is of size

MMC_BLEN:BLEN (block length value). This value must be set with the num-

ber of blocks – 1.

This register must be programmed prior to any multiple block data transfer. A

write into this register initializes an 11-bit counter that decrements by one after

each block transfer. A read into this register returns the number of blocks

remaining to be transferred to the card.

When the counter reaches 0, the transfer stops after the last transfer

For stream or multiple block transfer, a Block_RS interrupt is generated only

once after the last successful transfer when NBLK reaches 0.

In stream mode, the minimum allowable number of blocks is two blocks.

This value must be 0x000 for a single block transfer. In stream mode, the

minimum allowable number of blocks is two blocks. If the transfer is inter-

rupted by a STOP_TRANSMISSION command (CMD12) before the counter

reached 0, you must reprogram this register prior to starting any new single

or multiple block data transfers.

0x000: 1 block

0x7FF: 2048 blocks

Values after reset are low (all 11 bits).

MMC/SD Host Controller

MPU Public Peripherals