Emif Slow Chip-Select Configuration Registers - Texas Instruments OMAP5910 Technical Reference Manual

Table 4–13. EMIF Slow Chip-Select Configuration Registers
(EMIFS_CS0_CONFIG...EMIFS_CS3_CONFIG)
Bit Field
31–22 Reserved
21 FL
20 BW
19 Reserved
18:16 RDMODE
15:12 PGWST/WELEN
11:8 WRWST
The four EMIF slow chip-select configuration registers (see Table 4–13) are
used to select the protocols and timings to be used for handshake with devices
connected to CS0 - CS3 (corresponding to device pins FLASH.CS0 -
FLASH.CS3). Table 4–14 describes the memory types, and Table 4–15
describes the wait cycles insertion.
Value Description
Read is undefined. Writes must be zero.
Specifies how EMIFS handles addressing when
performing 32-bit writes to the OMAP5910 16-bit
data bus.
0 The address is incremented for the second 16-bit
access (default).
1 The address is not incremented for the second
16-bit access.
This bit is valid only when EMIFS is configured for
16-bit data bus width (BW = 0). This bit has no
effect for read operations.
Specifies EMIFS data bus width.
0 16-bit bus. This is the appropriate setting for
OMAP5910.
1 Reserved. Do not use this setting on OMAP5910.
(BW bit reset value depends on the chip-select: For
CS0 and CS3, BW = 0; For CS1 and CS2, BW = 1.
If CS1 or CS2 is to be used, BW must first be
written to 0 since OMAP5910 only supports 16-bit
bus.)
Read is undefined. Writes must be zero.
Read mode select (see Table 4–14)
For read accesses, number of wait states for page
mode ROM reads within a page. For write
accesses, the length of WE pulse duration.
Numbers of wait states for write operation
Traffic Controller Memory Interface Registers
Memory Interface Traffic Controller
Reset
Access
Value
R All 0
R/W 0
R/W
R 0
R/W 000
R/W 1111
R/W 1111
4-45