Device Types Associated With Chip-Select; Memory Map - Texas Instruments OMAP5910 Technical Reference Manual

Memory Map

4.2 Memory Map
Table 4–2. Device Types Associated With Chip-Select
4-6
Four external chip-selects and a series of internal address decodes are
provided for external and internal memories and for peripherals attached to the
TI peripheral bus (see Table 4–2). CS0, CS1, CS2, and CS3 each has an
address range of 32M bytes; the external SDRAM space has an address range
of 64M bytes; the internal SRAM space has an address range of 512K bytes.
In the boot overlay mode, CS0 and CS3 are swapped so that the MPU can boot
from a boot flash. Boot overlay mode is entered if pin MPU_BOOT is high dur-
ing reset (the state on the MPU_BOOT signal can change after reset). The
state of this pin is reflected in the BM bit field of the EMIF slow interface
configuration register. For details, see Table 4–12, EMIF Slow Interface
Configuration Register (EMIFS_CONFIG_REG).
CS Device
CS0 External asynchronous RAM
External asynchronous ROM or flash
External synchronous burst flash
CS1 External asynchronous RAM
External asynchronous ROM or flash
External synchronous burst flash
CS2 External asynchronous RAM
External asynchronous ROM or flash
External synchronous burst flash
CS3 External asynchronous RAM
External asynchronous ROM or flash
External synchronous burst flash
†
None External synchronous dynamic RAM
†
None Internal SRAM
† The interface to these memory devices is activated via internal address decoding. There is no
external chip select.
The OMAP5910 peripherals are mapped on the MPU memory space in two
different segments: through STROBE0 (public peripherals) and STROBE1
(private peripherals). Each peripheral has a range of 2K bytes.
Table 4–3 shows the MPU memory map.