32-Khz Timer Registers; Read/Write Synchronization - Texas Instruments OMAP5910 Technical Reference Manual

32-kHz Timer
7.5.2

32-kHz Timer Registers

Table 7–36. 32-kHz Timer Registers
Name Description
CR Timer control
TVR Tick value
TCR Tick counter
7.5.2.1 Synchronization Issues
Table 7–37. Read/Write Synchronization
Register Name
CR
TCR
TVR
7-48
Base address for 32-kHz timer: FFFB:9000
Table 7–36 lists the 32-kHz timer registers. Table 7–38 through Table 7–40
describe the individual registers.
Synchronization of reads and writes to the 32-kHz clock is done in different
ways for each register. This leads to slight restrictions concerning register
access (see Table 7–37).
Read
Can be read anytime. The value read
is the last value written.
Reads are resynchronized on
MPUXOR_CK clock to prevent
peripheral bus from timing out. Can
be read anytime, providing
MPUXOR_CK is running. If not, the
value is not guaranteed. Software
must wait one 32-kHz period after
turning on the MPUXOR_CK clock
before the TCR register can be read.
Can be read anytime. The value read
is the last value written
R/W Size Address
R/W 32 bits FFFB:9000
R/W 32 bits FFFB:9000
R 32 bits FFFB:9000
Write
Two consecutive writes must be separated
by at least 1 CLK32 period (31 µs). If this is
not the case, the value written is not
guaranteed
Writing to this has no effect.
Two consecutive writes must be separated
by at least 1 CLK32 period (31 µs). If this is
not the case the value written is not
guaranteed
Offset
0x08
0x00
0x04