Lcd One Frame Mode Transfer Scheme; Imif Lcd Register Settings-Two Frames - Texas Instruments OMAP5910 Technical Reference Manual

LCD Dedicated Channel
Figure 5–11.LCD One Frame Mode Transfer Scheme
5.4.4.2 IMIF to LCD, Two Frames
Table 5–8. IMIF LCD Register Settings—Two Frames
5-30
The transfer runs, and an interruption is generated at the end of the frame.
0x0B 0000
Video frame
0x0B 00DE
When an interrupt occurs, read the DMA_LCD_CTRL register to find the
source of the interrupt.
If DMA_LCD_CTRL(3) = 1, end frame 1 interrupt.
If end of frame is reached, the DMA restarts at the top of the frame. Reset
DMA_LCD_CTRL(3) and wait for another interrupt.
Figure 5–12 shows a transfer from two video frames located in IMIF to the LCD
controller. The size for the LCD display is 6 x 16 pixels with 16 bits per pixel.
So the length of one video frame is:
6 x 16 x 2 (in bytes) + 32 bytes for the palette = 224 bytes
If the video frame 1 starts at address 0x0B0000, the bottom address of the
video frame is 0x0B00DE. If the video frame 2 starts at address 0x0C0000, the
bottom address of the video frame is 0x0C00DE.
Registers settings are shown in Table 5–8.
DMA_LCD_CTRL
Frame_mode
Frame_it_ie
Bus_error_ie
Lcd_source
DMA_LCD_TOP_F1_U
SDRAM
lcd_top_frame1
DMA
lcd_bot_frame1
LCD
controller
Register Settings
1 (two frame)
1
1
1 (IMIF)
0x000B