Emif Global Reset Register (Emif Grr) - Texas Instruments OMAP5910 Technical Reference Manual

3.7.2

EMIF Global Reset Register (EMIF GRR)

3.8 DSP Memory Management Unit
Any write in the EMIF global reset register (GRR) register brings about a soft-
ware reset of the EMIF state machines. This register cannot be read. A soft-
ware reset does not change the current configuration register values
(EMIF_GCR , etc.); only the EMIF state machines are reset. The EMIF GRR
appears at word address 0x0801 in the DSP I/O space.
The DSP MMU maps the 16M bytes of the DSP virtual external addresses to
anyplace in the 4G-byte address space of the OMAP5910 device. At reset the
MMU is disabled and the DSP external memory space is mapped to the first
16M bytes of CS0 system memory.
The DSP MMU performs translation of 24-bit DSP external addresses
(028000 to FF8000 or FFFF00) to physical addresses in the 32-bit MPU
address space. Address translation is performed by a translation table struc-
ture (TTB) that maps the most significant bits of the DSP byte address onto
another set of most significant bits of a 32-bit MCU byte address. The least sig-
nificant bits of the DSP-generated byte address are not altered when forming
the new address. The TTB translations are expedited by a cache-like transla-
tion look-aside buffer mechanism (TLB). The address mapping may be
programmed at the TTB level or by writing the TLB entries directly. The DSP
MMU contains 32 TLB entries that can be configured to remap 1M-byte, 64K-
byte, 4K-byte, or 1K-byte segments of memory.
The DSP MMU is programmed by the TI925T. In general, the MMU is initialized
at boot time, but it also can be reprogrammed dynamically. The MMU is
programmed through the TIPB registers. DSP MMU registers have an MPU
base address of 0xFFFE:D200.
The MPU is responsible for configuration of the MMU. See Section 2.8, DSP
Memory Management Unit, for complete details on MMU configuration and
control.
EMIF / DSP Memory Management Unit DSP Memory Management Unit
DSP Subsystem 3-37