Mask Interrupt Register (Mir); Interrupt Input Register (Itr) - Texas Instruments OMAP5910 Technical Reference Manual

Table 8–23. Interrupt Input Register (ITR)
Bit Name
15 IRQ_15
::: :::
0 IRQ_0
Table 8–24. Mask Interrupt Register (MIR)
Bit Name
15 IRQ_15_MSK
::: :::
0 IRQ_0_MSK
In the event of an edge-sensitive interrupt, ITR stores an incoming interrupt.
When the DSP accesses the SIR_FIQ register, the bit corresponding to the
interrupt that has requested the DSP action is reset.
The DSP can also clear each bit individually by writing a 0 to the corresponding
bits at the ITR address. A 1 bit keeps its previous value. If the individual bit is
cleared just before the DSP unmasks the interrupts, the interrupt is not
processed.
The DSP reads this register. If an incoming interrupt is edge sensitive, the read
value corresponds to the value held in the storage element.
IRQ (FIQ) output and SIR_IRQ (SIR_FIQ) registers are reset only if the
bit of ITR register corresponding to the interrupt that requested DSP
action is already cleared or masked.
The time when this ITR bit is reset depends on the sensitivity of the
incoming interrupt. In case of an edge-sensitive interrupt, the IT register
bit is cleared when reading SIR_IRQ (SIR_FIQ) register. Otherwise, it is
reset when the corresponding interrupt line becomes inactive (low).
For a level-sensitive interrupt, the level must be removed before the write
to the control register. Otherwise, the interrupt controller is not reset for
a new interrupt.
Description
Disable IRQ_15 interrupt
:::
Disable IRQ_0 interrupt
Each incoming interrupt can be masked individually by this register by setting
the corresponding bit to 1.
Interrupt Handlers
Type
R/W
:::
R/W
Type
R/W
:::
R/W
DSP Private Peripherals
Reset
Value
0
:::
0
Reset
Value
1
:::
1
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