Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1421

ADSP-SC58x USB Trigger List
Table 27-4: ADSP-SC58x USB Trigger List Masters
Trigger ID Name
72 USB0_DATA
73
USB1_DATA
Table 27-5: ADSP-SC58x USB Trigger List Slaves
Trigger ID Name
USB Block Diagram
The USB OTG Controller Block Diagram shows the functional blocks within the USB. For more information about
the blocks, see the USB Functional
Figure 27-1: USB OTG Controller Block Diagram
USB Definitions
A list of common USB terms and their definitions as used in this specification and based on the USB controller
follows:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
USB0 DMA Status/Transfer Complete
USB1 DMA Status/Transfer Complete
Description
None
Description.
SYSTEM CLOCK
INTERRUPTS
AND RESET
INT/CLK MMR SLAVE DECODE
CONTROL AND DATA MUX
CPU
INTERFACE
INTERRUPT COMMON
REGISTERS REGISTERS
TRANSMIT (Tx) RECEIVE (Rx)
ENDPOINTS ENDPOINTS
ENDPOINT
CONTROL
SRP WAKEUP
DETECTION
ASYNC
WAKEUP
INTERRUPT
VBUS CONTROL
UTMI INTERFACE
TO PHY
UTMI PHY CLK
SLAVE
INTERFACE
TX EP COUNT MMR
REGISTERS SLAVE
FIFO DECODE DMA
AND ARB REGISTERS
HOST TRANSACTION CPU-SIDE
SCHEDULER BUFFERS
ENDPOINT CONTROL USB-SIDE
AND COMBINE BUFFERS
MAIN HNP/SRP
PACKET
PROTOCOL
ENCODE/
FSM
HS
DECODE
NEGOTIATE
UTMI
DATA SYNC
SYNC AND
CRC
PROTOCOL
GENERATE/
ENGINE TIMERS
CHECK
USB Functional Description
Sensitivity
Level
Level
Sensitivity
MASTER
INTERFACE
MASTER
CONTROL
DMA
CONTROLLER
DMA
CHANNELS
RAM
INTERFACE
CYCLE/PTR
CONTROL
ENDPOINT
RAM
PACKET
CONTROL
27–9