Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1427

After the first packet is unloaded, clear the USB_EP[n]_RXCSR_P.RXPKTRDY bit to allow reception of further
packets. If the USB_EP[n]_RXCSR_P.AUTOCLR bit is set and a maximum-sized packet is unloaded from the
FIFO, the USB_EP[n]_RXCSR_P.RXPKTRDY bit is cleared automatically. For packet sizes less than the maxi-
mum, clear the USB_EP[n]_RXCSR_P.RXPKTRDY bit manually (for example by the processor core).
If the USB_EP[n]_RXCSR_P.FIFOFULL bit is set to 1 when USB_EP[n]_RXCSR_P.RXPKTRDY is
cleared, the USB controller first clears the USB_EP[n]_RXCSR_P.FIFOFULL bit. The controller then sets the
USB_EP[n]_RXCSR_P.RXPKTRDY bit again, indicating that there is another packet waiting in the FIFO for
unloading.
High-Bandwidth Isochronous or Interrupt Transactions
High-bandwidth isochronous or interrupt transactions use much the same protocol as other isochronous or inter-
rupt transactions. There are, however, some special features to conducting high-bandwidth transactions.
• When setting the maximum packet size handled by the endpoint in the USB_EP[n]_TXMAXP/
USB_EP[n]_RXMAXP
USB_EP[n]_TXMAXP.MULTM1 and USB_EP[n]_RXMAXP.MULTM1 bits.
The maximum number of transactions (2 or 3) also represents the maximum number of sections in which any
single high-bandwidth packet can be transferred. The configuration sets the maximum size of the packet to 2
or 3 times the maximum payload specified for the endpoint in the same register.
The maximum payload that can be sent in any transaction is 1K byte.
NOTE:
• When sending packets, set the USB_EP[n]_TXCSR_P.TXPKTRDY bit using the application software. Sim-
ilarly, when unloading packets from the receive endpoint FIFO, clear the
USB_EP[n]_RXCSR_P.RXPKTRDY bit using the application software.
The AutoSet and AutoClear functions cannot be used to set and clear these bits in high-band-
CAUTION:
width transactions.
• The transmission of packets as a number of sections introduces a further type of error – the transmission of
incomplete packets.
For transmit endpoints, transmitting incomplete packets principally applies when the interface is in peripheral
mode. It occurs when the transmission fails to receive enough IN tokens from the host to send all the parts of
the data packet. It can also apply to high-bandwidth interrupt transactions in host mode where the core does
not receive any response from the device to which the packet is transmitted. In both cases, the
USB_EP[n]_TXCSR_P.INCOMPTX bit is set.
For receive endpoints, an incomplete packet issue can occur. The PIDs of the received parts of the data packet
show that one or more parts of the data packet have not been received. When this event happens, the
USB_EP[n]_RXCSR_P.INCOMPRX bit is set. Usually this bit is set in peripheral mode. However, it can
also be set in host mode (using the USB_EP[n]_RXCSR_H.INCOMPRX bit). This event occurs when the
USB communicates with a device that fails to respond in accordance with the USB protocol.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers, set the maximum number of transactions per micro-frame using the
Peripheral Mode
27–15