Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1432

Peripheral Transfer Work Flows
When all the expected data packets have been received, software writes to the
the USB_EP0_CSR[n]_P.SPKTRDY bit and to set the USB_EP0_CSR[n]_P.DATAEND bit (indicating that
no more data is expected).
When the host moves to the status stage of the request, software generates another endpoint 0 interrupt to indicate
that the request has completed. No further action is required from the software; the interrupt is just a confirmation
that the request completed successfully.
If the command is an unrecognized command, or cannot be executed, then when the host decodes it, software must
write to the
USB_EP0_CSR[n]_P
the USB_EP0_CSR[n]_P.SENDSTALL bit. When the host sends more data, the USB controller sends a stall to
tell the host that the request was not executed. Software generates an endpoint 0 interrupt and the
USB_EP0_CSR[n]_P.SENTSTALL bit is set.
If the host sends more data after the USB_EP0_CSR[n]_P.DATAEND has been set, then the USB controller
sends a stall. Software generates an endpoint 0 interrupt and the USB_EP0_CSR[n]_P.SENTSTALL bit is set.
Read Requests
The function sends the 8-byte command followed by read requests containing a packet (or packets) of data to the
host. Examples of standard device requests for read are:
• GET_CONFIGURATION
• GET_INTERFACE
• GET_DESCRIPTOR
• GET_STATUS
• SYNCH_FRAME
As with all requests, the sequence of events begins when the software receives an endpoint 0 interrupt. The
USB_EP[n]_RXCSR_P.RXPKTRDY bit is also set. The host then reads and decodes the 8-byte command from
the endpoint 0 FIFO. Write the USB_EP0_CSR[n]_P.SPKTRDY bit (indicating that the command has been
read from the FIFO).
The data to transmit to the host is written to the endpoint 0 FIFO. If the size of the transmit data is greater than the
maximum packet size for endpoint 0, only the maximum packet size is written to the FIFO. The
USB_EP0_CSR[n]_P.TXPKTRDY bit is then set (indicating that there is a packet in the FIFO to be sent).
When the packet has been sent to the host, software generates another endpoint 0 interrupt. The next data packet
can be written to the FIFO.
When the last data packet has been written to the FIFO, software writes to the
set the USB_EP0_CSR[n]_P.TXPKTRDY bit and to set the USB_EP0_CSR[n]_P.DATAEND bit. (This ac-
tivity indicates that there is no more data after this packet.)
When the host moves to the status stage of the request, software generates another endpoint 0 interrupt to indicate
that the request has completed. No further action is required from the software; the interrupt is just a confirmation
that the request completed successfully.
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register. This operation sets the USB_EP0_CSR[n]_P.SPKTRDY bit and
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
USB_EP0_CSR[n]_P
USB_EP0_CSR[n]_P
register to set
register to