Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1439

Figure 27-8: Endpoint 0 Rx Mode
Peripheral Mode, Bulk IN, Transfer Size Known
For this process, the maximum size of an individual packet (MaxPktSize) in bytes and the complete transfer size
(TxferSize) in bytes, must be known.
1. Load MaxPktSize into the
2. Set the following bits: USB_EP[n]_TXCSR_P.DMAREQEN = 1, USB_EP[n]_TXCSR_P.AUTOSET = 1,
USB_EP[n]_TXCSR_P.ISO = 0, USB_EP[n]_TXCSR_P.FRCDATATGL= 0.
3. Load the TxferSize value into the
4. Configure the DMA controller to write the data into the corresponding Tx FIFO address.
5. On each USB_DMA[n]_CNT
USB_EP[n]_TXCSR_P.TXPKTRDY bit is automatically set when each new packet is written.
ADDITIONAL INFORMATION: Repeat Step 5 for each full packet of the transfer. Even if the final packet is a
short packet, the USB controller automatically detects the packet because the
USB_EP[n]_TXCSR_P.TXPKTRDY bit is set.
Peripheral Mode, Bulk IN, Transfer Size Unknown
For this process, assume the maximum individual packet size (MaxPktSize) in bytes is an even number of bytes.
1. Load MaxPktSize into the
2. Set the following bits: USB_EP[n]_TXCSR_P.DMAREQEN = 1, USB_EP[n]_TXCSR_P.AUTOSET = 1,
USB_EP[n]_TXCSR_P.ISO = 0, USB_EP[n]_TXCSR_P.FRCDATATGL= 0.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
RX MODE
YES
RXPKTRDY
SET?
READ COUNT0
REGISTER (n)
UNLOAD n BYTES
FROM FIFO
LAST
PACKET
YES
SET SERVICEDRXPKTRDY
AND DATAEND
STATE = IDLE
RETURN
USB_EP[n]_TXMAXP
USB_DMA[n]_CNT
transition, the DMA controller writes a new packet into the FIFO. The
USB_EP[n]_TXMAXP
NO
RETURN
NO
SET
SERVICEDRXPKTRDY
register.
register.
register.
Peripheral Transfer Work Flows
27–27