Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1434

Peripheral Transfer Work Flows
Endpoint 0 States
When the USB operates as a peripheral, the endpoint 0 control has three modes (IDLE, Tx, and Rx). The modes
correspond to the phases of the control transfer and the state that endpoint 0 enters during phases of the transfer.
(See Endpoint 0 Service Routine as
IDLE is the default mode on power-up or reset. The processor sets RxPktRdy bit when endpoint 0 is in IDLE
state, indicating a new device request. Once the processor unloads the device request from the FIFO, the USB de-
codes the descriptor. It determines whether there is a data phase and, if so, the direction of the data phase of the
control transfer (to set the FIFO direction).
Depending on the direction of the data phase, endpoint 0 goes into either Tx state or Rx state. If there is no data
phase, endpoint 0 remains in IDLE state to accept the next device request.
The processor must take different actions at the different phases of the possible transfers (for example, loading the
FIFO, setting TxPktRdy). The Endpoint 0 Control States figure shows the actions for the phase. The USB
changes the FIFO direction depending on the direction of the data phase, independently of the processor.
Figure 27-4: Endpoint 0 Control States
Endpoint 0 Service Routine as Peripheral
The USB controller generates an endpoint 0 interrupt when:
• The USB controller sets the USB_EP0_CSR[n]_P.RXPKTRDY bit after a valid token has been received
and data has been written to the FIFO.
27–22
Peripheral.)
Sequence #1
TX State
Idle
IN Data
Setup
Phase
Sequence #1
Load FIFO and
CPU actions
Set TxPktRdy
Unload Device Request
and Clear RxPktRdy
Idle
OUT Data
Setup
Phase
Sequence #2
CPU actions
Unload Device Request
and Clear RxPktRdy
Sequence #3
(NO DATA Phase)
Setup
CPU actions
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Sequence #3
IDLE
Sequence #2
RX State
TX State Idle
. . .
IN Data IN Data Status Phase
Phase Phase (OUT)
. . .
Load FIFO and
Load FIFO and
Set TxPktRdy
Set TxPktRdy
and Set DataEnd
RX State Idle
. . .
OUT Data OUT Data Status Phase
Phase Phase (IN)
. . .
Unload FIFO and
Unload FIFO and
Clear RxPktRdy
Clear RxPktRdy
and Set DataEnd
Unload FIFO and
Clear RxPktRdy
Idle
Status Phase
(IN)
Unload Device Request
and Clear RxPktRdy
and Set DataEnd