Texas Instruments OMAP5912 Reference Manual page 1217

UARTs
Table 69. Line Status Register (LSR) (UART Mode)
Bit Name
7 RX_FIFO_STS
6 TX_SR_E
5 TX_FIFO_E
4 RX_BI
3 RX_FE
2 RX_PE
1 RX_OE
0 RX_FIFO_E
152 Serial Interfaces
Function
0: Normal operation.
1: At least one parity error, framing error, or break
indication in the receiver FIFO. Bit 7 is cleared
when no more errors are present in the FIFO.
0: Transmitter hold and shift registers are not
empty.
1: Transmitter hold and shift registers are empty.
0: Transmit hold register is not empty.
1: Transmit hold register is empty. The processor
can now load up to 64 bytes of data into the THR if
the TX FIFO is enabled.
0: No break condition.
1: A break was detected while the data being read
from the RX FIFO was being received (that is, RX
input was low for one character time frame).
0: No framing error in data being read from RX
FIFO.
1: Framing error occurred in data being read from
RX FIFO (received data did not have a valid stop
bit).
0: No parity error in data being read from RX FIFO.
1: Parity error in data being read from RX FIFO.
0: No overrun error.
1: Overrun error has occurred. Set when the
character held in the receive shift register is not
transferred to the RX FIFO. This case occurs only
when receive FIFO is full.
0: No data in the receive FIFO.
1: At least one data character in the RX_FIFO.
When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the
character at the top of the RX FIFO (next character to be read). Therefore,
reading the LSR, and then reading the RHR, identifies errors in a character.
Reading RHR updates [BI, FE, PE] (See Table 109, UART Mode Interrupts.)
LSR [7] is set when there is an error anywhere in the RX FIFO, and is cleared
only when there are no more errors remaining in the FIFO.
R/W Reset
R 0
R 1
R 1
R 0
R 0
R 0
R 0
R 0
SPRU760B