Texas Instruments OMAP5912 Reference Manual page 1213

UARTs
Table 63. UART IrDA Registers (Continued)
Address Registers
Offset
LCR[7] = 0
READ
0x16 x S SYSS
0x17 x S WER
†
In UART modes, IER[7:4] can only be written when EFR[4] = 1. In IrDA modes, EFR[4] has no effect on access to IER[7:4].
‡
MCR[7:5] and FCR[5:4] can only be written when EFR[4] = 1.
§
Transmission control register (TCR) and trigger level register (TLR) are accessible only when EFR[4] = 1 and MCR[6] = 1.
Table 64. Receive Holding Register (RHR)
Bit Name
7:0 RHR
Table 65. Transmit Holding Register (THR)
Bit Name
7:0 THR
148 Serial Interfaces
LCR[7] = 1 and
LCR[7:0] is not 0xBF
WRITE READ
SYSS SYSS
WER WER
Offset Address (hex): 0x00 x S and LCR[7] = 0 and read
The receiver section consists of the receiver holding register (RHR) and the
receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift
register receives serial data from RX input. The data is converted to parallel
data and moved to the RHR. If the FIFO is disabled, location 0 of the FIFO is
used to store the single data character.
If an overflow occurs the data in the RHR is not overwritten.
Function
Receive holding register
Offset Address (hex): 0x00 x S and LCR[7] = 0 and write
The transmitter section consists of the transmit holding register (THR) and the
transmit shift register. The transmit holding register is actually a 64-byte FIFO.
The LH writes data to the THR. The data is placed into the transmit shift
register where it is shifted out serially on the TX output. If the FIFO is disabled,
location 0 of the FIFO is used to store the data.
Function
Transmit holding register
Offset Address (hex): 0x02 x S and LCR not 0xBF (and EFR[4] = 1 for
FCR[5:4]) and write.
LCR[7:0] = 0xBF
WRITE READ
SYSS SYSS
WER WER
WRITE
SYSS
WER
R/W Reset
R Unknown
R/W Reset
W Unknown
SPRU760B