Texas Instruments OMAP5912 Reference Manual page 1385

Table 45. Non-ISO Endpoint Interrupt Status Register (EPN_STAT)
Bit Name
15:12 Reserved
11:8 EPn_RX_IT_SRC
7:4 Reserved
3:0 EPn_TX_IT_SRC
SPRU761A
Description
Reserved
The receive endpoint interrupt source (non-ISO) bit only concerns non-ISO
endpoints. When the IRQ_SRC.EPn_RX flag is set, the endpoint causing the
interrupt condition is encoded in these four register bits. When the
IRQ_SRC.EPn_RX flag is cleared, the four bits read as 0.
0000: No receive endpoint interrupt is pending.
0001: EP1
...
1111: EP15
Values after MPU or USB reset are low (all four bits).
Reserved
Transmit endpoint interrupt source (non-ISO) bit only concerns non-ISO
endpoints.When the IRQ_SRC.EPn_TX flag is set, the endpoint that causes this
flag to be set is encoded in these four register bits. When the IRQ_SRC.EPn_TX
flag is cleared, the four bits read as 0.
0000: No transmit endpoint interrupt is pending.
0001: EP1
...
1111: EP15
Values after MPU or USB reset are low (all 4 bits).
This read-only register identifies the non-ISO endpoint causing an EPn
interrupt. A write into it is denied.
Note:
If a nontransparent transaction occurs before a previous one on another end-
point in the same direction, the second interrupt is asserted only after the
USB device controller clears the first one and EPN_STAT is updated with the
corresponding interrupt assertion.
USB Device Controller
Universal Serial Bus (USB) 93