Texas Instruments OMAP5912 Reference Manual page 1215

UARTs
Table 67. Supplementary Control Register (SCR)
Bit Name
7 RX_TRIG_GRANU1
6 TX_TRIG_GRANU1
5 DSR_IT
4 RX_CTS_DSR_
WAKE_UP_ENABLE
3 TX_EMPTY_CTL_IT
2:1 DMA_MODE_2
0 DMA_MODE_CTL
150 Serial Interfaces
Offset Address (hex): 0x10 x S
Function
0: Disables the granularity of 1 for trigger RX level.
1: Enables the granularity of 1 for trigger RX level.
0: Disables the granularity of 1 for trigger TX level.
1: Enables the granularity of 1 for trigger TX level.
0: Disables DSR interrupt.
1: Enables DSR interrupt.
0: Disables the wake-up interrupt and clears
SSR[1].
1: Waits for a falling edge of pins RX, CTS or DSR
to generate an interrupt.
0: Normal mode for THR interrupt (See UART mode
interrupts table.)
1: The THR interrupt is generated when TX FIFO
and TX shift register are empty.
Used to specify the DMA mode valid if SCR[0] = 1
00: DMA mode 0 (no DMA)
01: DMA mode 1 (UART_nDMA_REQ[0] in TX,
UART_nDMA_REQ[1] in RX)
10: DMA mode 2 (UART_nDMA_REQ[0] in RX)
11: DMA mode 3 (UART_nDMA_REQ[0] in TX)
0: The DMA_MODE is set with FCR[3].
1: The DMA_MODE is set with SCR[2:1].
Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the
IIR register. Therefore, when an interrupt occurs and there is no interrupt
pending in the IIR register, the SSR[1] bit must be checked. To clear the
wake-up interrupt, bit SCR[4] must be reset to 0.
Offset Address (hex): 0x03 x S
LCR[6:0] defines parameters of the transmission and reception.
R/W Reset
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 00
R/W 0
SPRU760B