Texas Instruments OMAP5912 Reference Manual page 1319

Table 1. USB Host Controller Registers (Continued)
Name
Reserved
HOSTUEADDR
HOSTUESTATUS
HOSTTIMEOUTCTRL
HOSTREVISION
Reserved
† Access to these registers must be by 32-bit reads or 32-bit writes. Use of other access sizes may result in undefined operation.
‡ Restrictions apply to the physical addresses used in these registers. See Section 2.9, Physical Addressing.
§ This register provides control and status for the OMAP5912 pins normally associated with USB port 0 (the integrated USB
transceiver) for some HMC_MODE values.
¶ This register provides control and status for the OMAP5912 pins normally associated with USB port 1 for some HMC_MODE
values.
# This register provides control and status for the OMAP5912 pins normally associated with USB port 2 for some HMC_MODE
values.
Table 2. OHCI Revision Number Register (HCREVISION)
Bit Name
31:8 Reserved
7:0 REV
Table 3. HC Operating Mode Register (HCCONTROL)
Bit Name
31:11 Reserved
10 RWE
SPRU761A
Description
Reserved
Host UE address
Host UE status
Host time-out control
Host revision
Reserved
The OCHI revision number (Table 2) register reports the revision number of
the OHCI Specification for USB upon which the USB host controller is based.
Description
Reserved
OHCI specification revision—the OHCI revision
number upon which the USB host controller is based.
Write has no effect.
The HC operating mode register (Table 3) controls the operating mode of the
USB host controller.
Value Description
Reserved
Remote wake-up enable. This bit has no effect in
OMAP5912. The OMAP5912 USB host controller does
not provide a processor wake-up mechanism.
USB Host Controller
†
R/W Size
None FFFB:A060h to
FFFB:A0DFh
R 32 FFFB:A0E0h
R 32 FFFB:A0E4h
R/W 32 FFFB:A0E8h
R 32 FFFB:A0ECh
None FFFB:A0F0h to
FFFB:AFFFh
Type
R
Type
R/W
Universal Serial Bus (USB)
Address
Reset
0x00 0000
0x10
Reset
0
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