Texas Instruments OMAP5912 Reference Manual page 1349

Table 25. HC Port 3 Status and Control Register (HCRHPORTSTATUS3)
(Continued)
Bit Name
8 PPS/SPP
7:5 Reserved
4 PRS/SPR
3 POCI/CSS
SPRU761A
Description
Port 3 power status/set port power
This bit indicates, when read as 1, that the port 3 power is
enabled. When read as 0, port 3 power is not enabled.
The OMAP5912 does not provide signals from the USB host
controller to control external port power, so, if required, USB
host port power control signals must be controlled through
other means. Software can track the current power state
using the port power status bit and other power control bits,
but those bits have no direct effect on external port power
control.
A write of 1 to this bit sets the port 3 power status bit. A write
of 0 has no effect.
This bit has no relationship to the OTG controller register bits
that relate to VBUS. System software can update this register
to simplify host controller driver and/or OTG driver coding.
Reserved
Port 3 reset status/set port reset
When read as 1, indicates that port 3 is sending a USB reset.
When read as 0, USB reset is not being sent to port 3.
A write of 1 to this bit sets the port 3 reset status bit and
causes the USB host controller to begin signaling USB reset
to port 3. A write of 0 to this bit has no effect.
Port 3 overcurrent indicator/clear suspend status
When read as 1, indicates that a port 3 overcurrent condition
has occurred. When 0, no port 3 overcurrent condition has
occurred.
The OMAP5912 does not provide inputs for signaling
external overcurrent indication to the USB host controller.
Overcurrent monitoring, if required, must be handled through
some other mechanism.
A write of 1 to this bit when port 3 suspend status is 1 causes
resume signaling on port 3. A write of 1 when port 3 suspend
status is 0 has no effect. A write of 0 has no effect.
This bit has no relationship to the OTG controller register bits
that relate to VBUS.
USB Host Controller
Type
R/W
R/W
R/W
Universal Serial Bus (USB)
Reset
1
0
0
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