Texas Instruments OMAP5912 Reference Manual page 1313

Multimedia processor device overview and architecture
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Figure 1.
USB Host Controller
Traffic
controller
ROM
16,32
SRAM
Flash
Slow
SBFlash
bus
16
SDRAM
Fast
bus
32
L3/OCP-T1
(target)
32
L3/OCP-T2
(target)
32
L3/OCP-I
(initiator)
interconnect
USB power
switching
USB
USB
connector
connector
SPRU761A
To DSP MMU
To DSP MMU
S
L
MPU bus
32
O
W
32
Slow I/F DMA
I/F
F
A
32
Fast I/F DMA
S
T
32
I/F
32
L3/OCP-T1 DMA
L3
O
C
32
P
I/F
L3/OCP-T2 DMA
L3
O
C
P
I/F
ARM926EJS
32
plus IF logic
L3/OCP
initiator
USB host controller
Local bus
32
OCP
Signals to/from other
peripherals
Top-level pin
GPIO
USB
transceiver,
ESD
protection
USB
connector
To MPUI
32
32
32
MPUI-DMA
Slow
port
port
Fast
port
TIPB
System
port
DMA
controller
OCP-T1
port
OCP-T2
TIPB
port
I/F
32
32
MPU
MPU bus
32
MPU pubic
peripheral
bus
interface
interface
OHCI controller
USB signal multiplexing
USB
transceiver
multiplexing
USB
transceiver,
ESD
protection
Universal Serial Bus (USB)
USB Host Controller
T
I
32
MPU
P
TIPB
(pubic)
B
32
32
MPU
b
TIPB
(private)
r
i
d
MPU
g
TIPB
e
(2)
32
MPU shared
peripherals
MPU pubic
peripheral bus
INTH2
USB
function
controller
UART 1
ESD
protection
21

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