Texas Instruments OMAP5912 Reference Manual page 1228

Table 89. TX FIFO Trigger Level Setting Summary
SCR[6] TLR[3:0]
0 0000
0 Non-zero
1 Value
Table 90. RX FIFO Trigger Level Setting Summary
SCR[7] TLR[7:4]
0 0000
0 Non-zero
1 Value
Table 91. Mode Definition Register 1 (MDR1)
Bit Name
7 FRAME_END_MODE
6 SIP_MODE
SPRU760B
Table 89 and Table 90 summarize the different ways to set the trigger levels
for the transmit FIFO and the receive FIFO, respectively.
TX FIFO Trigger Level
Defined by FCR[5:4] (either 8,16,32, 56 spaces)
Defined by TLR[3:0] (from 4 to 60 spaces with a granularity of 4 spaces)
Defined by the concatenated value of TLR[3:0] and FCR [5:4] (from 1 to 63 spaces
with a granularity of 1 space).
Note: The combination of TLR [3:0] = 0000 and FCR [5:4] = 00 (all zeros) is not
supported (min 1 space required). All zeros result in unpredictable behavior.
RX FIFO Trigger Level
Defined by FCR[7:6] (either 8,16,56, 60 characters)
Defined by TLR[7:4] (from 4 to 60 characters with a granularity of 4 characters)
Defined by the concatenated value of TLR[7:4] and FCR [7:6] (from 1 to 63
characters with a granularity of 1 character)
Note: The combination of TLR[7:4] = 0000 and FCR [7:6] = 00 (all zeros) is not
supported (min 1 character required). All zeros result in unpredictable behavior.
Offset Address (hex): 0x08 x S
The mode of operation is programmed by writing to MDR1[2:0]. Therefore, the
MDR1 must be programmed on start-up after configuring registers DLL, DLH,
and LCR. The value of MDR1[2:0] must not be changed again during normal
operation.
Function
0: Frame-length method.
1: Set EOT bit method.
MIR/FIR modes only
0: Manual SIP mode: SIP is generated with the
control of ACREG[3].
1: Automatic SIP mode: SIP is generated after each
transmission.
UARTs
R/W Reset
R/W 0
R/W 0
Serial Interfaces 163