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Table 33. Endpoint Selection Register (EP_NUM)
Bit
Name
15:7
−
6
SETUP_SEL
5
EP_SEL
SPRU761A
Description
Reserved
The setup FIFO select bit is set by the USB device controller to access the status
(STAT_FLG, RXFSTAT) and data (DATA) registers for the endpoint selected. If
EP_NUM.EP_DIR bit is set to 0, the MPU can read data from endpoint RX FIFO
by reading DATA register. If EP_NUM.EP_DIR bit is set to 1, the MPU can write
data into endpoint TX FIFO by writing into the DATA register. After each access to
an endpoint during interrupt handling, the USB device controller must absolutely
clear this bit:
0: No access
1: Access permitted
Note: When the USB device controller sets this bit, it must set SETUP_SEL bit to
0. After having accessed the endpoint FIFO either for read or for write access, the
USB device controller must clear this bit by writing a 0 to it.
The value after MPU or USB reset is low.
The TX/RX FIFO select bit is set by the USB device controller in response to a
set-up general USB interrupt, to access the EP0 read-only setup FIFO when
reading DATA register. Setting this bit clears the IRQ_SRC.SETUP interrupt bit.
When this bit is set, the value of other EP_NUM register bits must be 0.
0: No access
1: Access permitted
Note: After having read the setup FIFO, the USB device controller must clear this
bit by writing a 0 to it.
Value after MPU or USB reset is low.
USB Device Controller
Universal Serial Bus (USB)
71
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