Texas Instruments OMAP5912 Reference Manual page 1368

USB Device Controller
Table 36. Status Register (STAT_FLG) (Continued)
Bit Name
12 ISO_ERR
11:10 −
9 ISO_FIFO_EMPTY
8 ISO_FIFO_FULL
7 -
6 EP_HALTED
76 Universal Serial Bus (USB)
Description
The isochronous receive data error (ISO OUT) bit only concerns ISO
OUT endpoints. When set, this bit indicates that the ISO data packet
was received incorrectly. This happens when the core detects an
error in the data packet (CRC, bit stuffing, PID check) or when there
is an overrun condition in the FIFO. When this bit is set, the FIFO
contents are automatically flushed by the core and the FIFO status is
empty.
This bit is updated in every frame.
0: Not significant
1: ISO packet received with errors
Value after MPU or USB reset is low.
Reserved
The ISO FIFO empty bit only concerns ISO endpoints.This bit is set
when the FIFO for the selected ISO endpoint is empty, either via an
appropriate CTRL.CLR_EP bit or CTRL.RESET_EP bit or after
successful reads from the selected FIFO.
0: ISO FIFO is not empty.
1: ISO FIFO is empty.
Value after MPU or USB reset is high (FIFO empty).
The ISO FIFO full bit only concerns ISO endpoints.This bit is set
when the FIFO for the selected ISO endpoint is full. This condition is
cleared by setting the CTRL.CLR_EP bit or CTRL.RESET_EP bit, or
after one successful read (by the USB device controller or the USB
host).
0: ISO FIFO is not full.
1: ISO FIFO is full.
Value after MPU or USB reset is low (FIFO empty).
Reserved
The endpoint halted flag (non-ISO) bit only concerns non-ISO
endpoints.This bit when asserted 1 indicates that the selected
endpoint is halted. The endpoint can be put into the halt state only by
the USB device controller writing the endpoint halt control bit (in
response to a SET_FEATURE request, for instance).
0: The selected endpoint is not halted.
1: The selected endpoint is halted.
Value after MPU or USB reset is low.
SPRU761A