Texas Instruments OMAP5912 Reference Manual page 1358

USB Host Controller
2.14 OCPI Registers
2.15 USB Host Controller Clock Control
2.16 USB Host Controller Hardware Reset
66 Universal Serial Bus (USB)
the DMA controller, peripherals connected to the OCPI bus can generate the
address, byte enables, and read/write indication for each OCPI access. This
functionality allows the USB host controller to implement a scatter-gather
engine to access the OHCI data structures from system memory in an efficient
manner.
The USB host controller connects to an OCPI arbiter, which then connects to
the transfer controller OCP-I port. There are no OCPI arbiter register settings
that affect USB host controller access to system memory, but the transfer
controller OCP-I port must be properly configured to allow access to system
memory.
Because the USB host must be able to access system memory, the
OMAP5912 security features must be properly configured to allow USB host
controller access to system memory.
The OMAP5912 clock generation and system reset management module
(ULPD) provides a 48-MHz clock to the USB OTG controller, USB device
controller, and USB host controller. This clock can be stopped by software to
reduce USB OTG controller, USB device controller, and USB host controller
power consumption when USB functionality is not needed.
The ULPD controls the 48-MHz clock to the USB host controller via:
-
CLOCK_CTRL_REG.USB_MCLK_EN
-
SOFT_REQ_REG.SOFT_USB_OTG_DPLL_REQ
-
SOFT_DISABLE_REQ_REG.DIS_USB_HOST_DPLL_REQ
When these ULPD register bits are properly configured, the USB host
controller receives a clock when the UHOST_EN signal is active. See
discussions of
OTG_SYSCON_2.HOST_EN in Section 4.
The USB host controller is held in reset and receives no clock at any time that
UHOST_EN is inactive.
The ULPD module provides reset of the USB host controller. The PER_EN bit
in the MPU reset control 2 register controls the reset to many OMAP5912
OT_SYSCON_2.OTG_PADEN and
SPRU761A