Texas Instruments OMAP5912 Reference Manual page 1317

2.4 USB Host Controller Registers
Table 1. USB Host Controller Registers
Name
HCREVISION
HCCONTROL
HCCOMMANDSTATUS
HCINTERRUPTSTATUS
HCINTERRUPTENABLE
HCINTERRUPTDISABLE
HCHCCA
† Access to these registers must be by 32-bit reads or 32-bit writes. Use of other access sizes may result in undefined operation.
‡ Restrictions apply to the physical addresses used in these registers. See Section 2.9, Physical Addressing.
§ This register provides control and status for the OMAP5912 pins normally associated with USB port 0 (the integrated USB
transceiver) for some HMC_MODE values.
¶ This register provides control and status for the OMAP5912 pins normally associated with USB port 1 for some HMC_MODE
values.
# This register provides control and status for the OMAP5912 pins normally associated with USB port 2 for some HMC_MODE
values.
SPRU761A
HCRHPORTSTATUS[n].PSS = 0 until after the approximately 3-ms delay
after resume signaling completes.
When using port-specific suspend, system software must ensure that there
are no active EDs for devices that are downstream of the suspended port
before setting the port into suspend mode. While the port is in suspend or being
resumed, system software must not enable any EDs for any devices
downstream of the suspended port. Once the root hub status change interrupt
occurs as a result of the suspended port PSS bit changing to 0, EDs can be
enabled for devices downstream of the port that is now operational.
Most of the OMAP5912 host controller (HC) registers are the OHCI
operational registers, which are defined by the OHCI Specification for USB.
Four additional registers not specified by the OHCI Specification for USB
provide additional information about the USB host controller state. USB host
controller registers can be accessed in user and supervisor modes.
The OMAP5912 USB host controller registers are listed in Table 1. Table 2
through Table 29 describe specific register bits.
Description
OHCI revision number
HC operating mode
HC command and status
HC interrupt status
HC interrupt enable
HC interrupt disable
Physical address of HCCA
R/W
R
R/W
R/W
R/W
R/W
R/W
‡
R/W
Universal Serial Bus (USB)
USB Host Controller
†
Size Address
32 FFFB:A000h
32 FFFB:A004h
32 FFFB:A008h
32 FFFB:A00Ch
32 FFFB:A010h
32 FFFB:A014h
32 FFFB:A018h
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