Texas Instruments OMAP5912 Reference Manual page 1398

Multimedia processor device overview and architecture
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USB Device Controller
Table 53. Receive Endpoint n Configuration Register (EPn_RX) (Continued)
Bit
Name
11
EPn_RX_ISO
10:0
EPn_RX_PTR
106
Universal Serial Bus (USB)
Description
The receive ISO endpoint n field must be set if the receive endpoint n type
is isochronous in the desired device configuration. If not set, the endpoint
type is bulk or interrupt (the hardware does not distinguish bulk type from
interrupt).
0: Receive endpoint n type is isochronous.
1: Receive endpoint n type is bulk or interrupt.
Values after USB device controller hardware reset or USB reset are
unchanged.
The receive endpoint n pointer field contains the address of the receive
endpoint n pointer. Value 0x000 is not permitted (reserved for setup FIFO).
Caution: For ISO endpoints or for non-ISO endpoints that allow
double-buffering, 2*RX buffer size must be reserved for ping-pong.
0x000: address = BASE (not permitted)
0x001: address = BASE + 8 bytes
0x002: address = BASE + 16 bytes
0x003: address = BASE + 24 bytes
...
0x0FF: address = BASE + 2040 bytes
Values after USB device controller hardware reset or USB reset are
unchanged (which means that values are unknown until first write access).
Note: Pointer value must be set to a value < 0xFF, because the memory
size is 2K bytes and a pointer coded value = 0xFF corresponds to 2040
bytes. Addressing upper bytes results in memory overlap.
This read/write register gives the device configuration for non-control receive
endpoint n (n: 115). The endpoints size fields must match values sent by the
USB
device
controller
GET_CONFIGURATION_DESCRIPTOR during configuration phase.
The
USB
device
SYSCON1.CFG_LOCK
SYSCON1.CFG_LOCK is set.
Values depend on whether the reset action comes from USB device controller
(MPU) or USB host.
to
the
USB
controller
must
fill
and
must
not
host
in
response
this
field
before
change
the
values
SPRU761A
to
the
setting
once

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