Texas Instruments OMAP5912 Reference Manual page 1218

Table 70. Line Status Register (LSR) (IR Mode)
Bit Name
7 THR_EMPTY
6 STS_FIFO_FULL
5 RX_LAST_BYTE
4 FRAME_TOO_LONG
3 ABORT
2 CRC
SPRU760B
Reading the LSR does not cause an increment of the RX FIFO read pointer.
The RX FIFO read pointer is incremented by reading the RHR.
Reading LSR clears [OE] if set (See Table 109, UART Mode Interrupts.)
Function
0: Transmit holding register is not empty.
1: Transmit holding register is empty. The
processor can now load up to 64 bytes of data into
the THR if the TX FIFO is enabled.
0: Status FIFO not full.
1: Status FIFO full.
0: The RX FIFO does not contain the last byte of
the frame to be read.
1: The RX FIFO contains the last byte of the frame
to be read. This bit is set only when the last byte
of a frame is available to be read. It is used to
determine the frame boundary. It is cleared on a
single read of the LSR register.
0: No frame-too-long error in frame.
1: Frame-too-long error in the frame at the top of
the STATUS FIFO, [next character to be read].
This bit is set to 1 when a frame exceeding the
maximum length (set by RXFLH and RXFLL
registers) has been received. When this error is
detected, current frame reception is terminated.
Reception is stopped until the next START flag is
detected.
0: No abort pattern error in frame.
1: Abort pattern is received.
SIR & MIR: Abort pattern
FIR: Illegal symbol 0000
0: No CRC error in frame.
1: CRC error in the frame at the top of the
STATUS FIFO (next character to be read).
UARTs
R/W Reset
R 1
R 0
R 0
R 0
R 0
R 0
Serial Interfaces 153