Texas Instruments OMAP5912 Reference Manual page 1212

Table 63. UART IrDA Registers
Address Registers
Offset
LCR[7] = 0
READ
0x00 x S RHR
0x01 x S IER §
0x02 x S IIR
0x03 x S LCR
0x04 x S MCR ‡
0x05 x S LSR
0x06 x S MSR/TCR
0x07 x S SPR/TLR †
0x08 x S MDR1
0x09 x S MDR2
0x0A x S SFLSR
0x0B x S RESUME
0x0C x S SFREGL
0x0D x S SFREGH
0x0E x S BLR
0x0F x S ACREG
0x10 x S SCR
0x11 x S SSR
0x12 x S EBLR
0x14 x S MVR
0x15 x S SYSC
†
In UART modes, IER[7:4] can only be written when EFR[4] = 1. In IrDA modes, EFR[4] has no effect on access to IER[7:4].
‡
MCR[7:5] and FCR[5:4] can only be written when EFR[4] = 1.
§
Transmission control register (TCR) and trigger level register (TLR) are accessible only when EFR[4] = 1 and MCR[6] = 1.
SPRU760B
LCR[7] = 1 and
LCR[7:0] is not 0xBF
WRITE READ
THR DLL
IER § DLH
FCR ‡ IIR
LCR LCR
MCR ‡ MCR
− LSR
† TCR † MSR/TCR
SPR/TLR † SPR/TLR
MDR1 MDR1
MDR2 MDR2
TXFLL SFLSR
TXFLH RESUME
RXFLL SFREGL
RXFLH SFREGH
BLR UASR
ACREG −
SCR SCR
− SSR
EBLR −
− MVR
SYSC SYSC
WRITE
DLL
DLH
FCR ‡
LCR
‡ MCR ‡
−
† TCR †
† SPR/TLR †
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
−
−
SCR
−
−
−
SYSC
LCR[7:0] = 0xBF
READ WRITE
DLL DLL
DLH DLH
EFR EFR
LCR LCR
XON1/ADDR1 XON1/ADDR1
XON2/ADDR2 XON2/ADDR2
XOFF1/TCR † XOFF1/TCR
XOFF2/TLR † XOFF2/TLR
MDR1 MDR1
MDR2 MDR2
SFLSR TXFLL
RESUME TXFLH
SFREGL RXFLL
SFREGH RXFLH
UASR −
− −
SCR SCR
SSR −
− −
MVR −
SYSC SYSC
Serial Interfaces
UARTs
†
†
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